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Preliminary GS8662D08/09/18/36E-333/300/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
* Simultaneous Read and Write SigmaQuadTM Interface * JEDEC-standard pinout and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * Burst of 4 Read and Write * 1.8 V +100/-100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ pin for programmable output drive strength * IEEE 1149.1 JTAG-compliant Boundary Scan * Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices * 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package * RoHS-compliant 165-bump BGA package available
72Mb SigmaQuad-II Burst of 4 SRAM
333 MHz-167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O SigmaQuad-II B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a SigmaQuad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).
SigmaQuadTM Family Overview
The GS8662D08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662D08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and
Parameter Synopsis
- 333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.50 ns
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
2M x 36 SigmaQuad-II SRAM--Top View
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 Doff D31 Q32 Q33 D33 D34 Q35 TDO 2 MCL/SA (288Mb) Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 SA D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 MCL/SA (144Mb) Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 2. MCL = Must Connect Low
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
4M x 18 SigmaQuad-II SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. MCL = Must Connect Low
Rev: 1.01a 2/2006
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(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
8M x 9 SigmaQuad-II SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 SA NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. 2. MCL = Must Connect Low
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
8M x 8 SigmaQuad-II SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. MCL = Must Connect Low
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Pin Description Table Symbol
SA NC R W BW0-BW3 NW0-NW1 K K C C TMS TDI TCK TDO VREF ZQ Qn Dn Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin
Description
Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Nybble Write Control Pin Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Synchronous Data Outputs Synchronous Data Inputs Disable DLL when low Output Echo Clock Output Echo Clock Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input -- Input Input Input Input Input Input Input Input Input Input Input Output Input Input Output Input Input Output Output Supply Supply Supply
Comments
-- -- Active Low Active Low Active Low x9/x18/x36 only Active Low x8 only Active High Active Low Active High Active Low -- -- -- -- -- --
Active Low -- -- 1.8 V Nominal 1.5 or 1.8 V Nominal --
Rev: 1.01a 2/2006
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(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM's bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II SRAMs follow a few simple rules of operation. - Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port. - Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM. - All address, data, and control inputs are sampled on clock edges. In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.
SigmaQuad-II B4 SRAM DDR Read The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.
SigmaQuad-II B4 Double Data Rate SRAM Read First
Read A NOP Read B Write C Read D Write E NOP
K K Address R W BWx D C C Q CQ CQ A A+1 A+2 A+3 B B+1 B+2 B+3 D D+1 D+2 C C C+1 C+1 C+2 C+2 C+3 C+3 E E E+1 E+1 A B C D E
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
SigmaQuad-II B4 SRAM DDR Write The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.
SigmaQuad-II B4 Double Data Rate SRAM Write First
Write A NOP Read B Write C Read D Write E NOP
K K Address R W BWx D C C Q CQ CQ B B+1 B+2 B+3 D D+1 D+2 A A A+1 A+1 A+2 A+2 A+3 A+3 C C C+1 C+1 C+2 C+2 C+3 C+3 E E E+1 E+1 E+ E+ A B C D E
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. 1b. 1c. Apply VDD. Apply VDDQ. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.
DLL Constraints
* The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 21). * The DLL cannot operate at a frequency lower than 119 MHz. * If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.
Power-Up Sequence (Doff controlled)
Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Power-Up Sequence (Doff tied High)
Power UP Interval Unstable Clocking Interval Stop Clock Interval 30ns Min DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Special Functions
Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0-D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, "Nybble Write Enable" and "NBx" may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2 Beat 3 Beat 4
BW0
0 1 0 1
BW1
1 0 0 0
D0-D8
Data In Don't Care Data In Don't Care
D9-D17
Don't Care Data In Data In Data In
Resulting Write Operation Byte 1 D0-D8
Written Beat 1
Byte 2 D9-D17
Unchanged
Byte 1 D0-D8
Unchanged Beat 2
Byte 2 D9-D17
Written
Byte 1 D0-D8
Written Beat 3
Byte 2 D9-D17
Written
Byte 1 D0-D8
Unchanged Beat 4
Byte 2 D9-D17
Written
Output Register Control SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Example Four Bank Depth Expansion Schematic
R3 W3 R2 W2 R1 W1 R0 W0 A0-An K D1-Dn Bank 0 A W R K D C C Q1-Qn CQ0 CQ1 CQ2 CQ3 CQ Q Bank 1 A W R K D C CQ Q Bank 2 A W R K D C CQ Q Bank 3 A W R K D C CQ Q
Note: For simplicity BWn, NWn, K, and C are not shown.
Rev: 1.01a 2/2006
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2x2B4 SigmaQuad-II SRAM Depth Expansion
Read A Write B Read C Write D Read E Write F NOP
Rev: 1.01a 2/2006
A B C D E F D D B B B+1 B+2 B+3 B+1 B+2 B+3 D+1 D+2 D+1 D+2 D+3 D+3 F F F+1 F+1 F F A A+1 A+2 A+3 E E+1 E+2 C C+1 C+2 C+3
K
K
Address
R(1)
R(2)
W(1)
W(2)
BWx(1)
D(1)
12/29
BWx(2)
D(2)
C[1]
C[1]
Q(1)
CQ(1)
CQ[1]
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
C[2]
C[2]
Q(2)
CQ[2]
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(c) 2005, GSI Technology
CQ[2]
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FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150 and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM's output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a "1" or is High-Z. Pull-up drive impedance is updated when a driver is producing a "0" or is High-Z.
Separate I/O SigmaQuad-II B4 SRAM Truth Table Previous Operation
K (tn-1)
A
K (tn)
R
K (tn)
W
K (tn)
Current Operation
K (tn)
D
K (tn+1)
D
K (tn+11/2)
D
K (tn+2)
D
K (tn+21/2)
Q
K (tn+1)
Q
K (tn+11/2)
Q
K (tn+2)
Q
K (tn+21/2)
Deselect Write Read Deselect Deselect Read Write
X X X V V V V
1 1 X 1 0 X 0
1 X 1 0 X 0 X
Deselect Deselect Deselect Write Read Write Read
X D2 X D0 X D0 D2
X D3 X D1 X D1 D3
-- -- -- D2 -- D2 --
-- -- -- D3 -- D3 --
Hi-Z Hi-Z Q2 Hi-Z Q0 Q2 Q0
Hi-Z Hi-Z Q3 Hi-Z Q1 Q3 Q1
-- -- -- -- Q2 -- Q2
-- -- -- -- Q3 -- Q3
Notes: 1. "1" = input "high"; "0" = input "low"; "V" = input "valid"; "X" = input "don't care" 2. "--" indicates that the input requirement or output state is determined by the next operation. 3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations. 4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. Users should not clock in metastable addresses.
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Byte Write Clock Truth Table BW
K (tn+1)
BW
K (tn+11/2)
BW
K (tn+2)
BW
K (tn+21/2)
Current Operation
K (tn)
D
K (tn+1)
D
K (tn+11/2)
D
K (tn+2)
D
K (tn+21/2)
T T F F F F
T F T F F F
T F F T F F
T F F F T F
Write Dx stored if BWn = 0 in all four data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Dx stored if BWn = 0 in 3rd data transfer only Write Dx stored if BWn = 0 in 4th data transfer only Write Abort No Dx stored in any of the four data transfers
D0 D0 X X X X
D2 X D1 X X X
D3 X X D2 X X
D4 X X X D3 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more BWn = 0, then BW = "T", else BW = "F".
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Preliminary GS8662D08/09/18/36E-333/300/250/200/167
x36 Byte Write Enable (BWn) Truth Table BW0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
BW1 BW2 BW3
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D0-D8
Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In
D9-D17
Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In
D18-D26
Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In
D27-D35
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Data In Data In Data In Data In
x18 Byte Write Enable (BWn) Truth Table BW0 BW1
1 0 1 0 1 1 0 0
D0-D8
Don't Care Data In Don't Care Data In
D9-D17
Don't Care Don't Care Data In Data In
x09 Byte Write Enable (BWn) Truth Table BW0
1 0 1 0
D0-D8
Don't Care Data In Don't Care Data In
Rev: 1.01a 2/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Nybble Write Clock Truth Table NW
K (tn+1)
NW
K (tn+11/2)
NW
K (tn+2)
NW
K (tn+21/2)
Current Operation
K (tn)
D
K (tn+1)
D
K (tn+11/2)
D
K (tn+2)
D
K (tn+21/2)
T T F F F F
T F T F F F
T F F T F F
T F F F T F
Write Dx stored if NWn = 0 in all four data transfers Write Dx stored if NWn = 0 in 1st data transfer only Write Dx stored if NWn = 0 in 2nd data transfer only Write Dx stored if NWn = 0 in 3rd data transfer only Write Dx stored if NWn = 0 in 4th data transfer only Write Abort No Dx stored in any of the four data transfers
D0 D0 X X X X
D2 X D1 X X X
D3 X X D2 X X
D4 X X X D3 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more NWn = 0, then NW = "T", else NW = "F".
x8 Nybble Write Enable (NWn) Truth Table NW0 NW1
1 0 1 0 1 1 0 0
D0-D3
Don't Care Data In Don't Care Data In
D4-D7
Don't Care Don't Care Data In Data In
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Preliminary GS8662D08/09/18/36E-333/300/250/200/167
State Diagram
Power-Up
Read NOP
READ
WRITE
Write NOP
READ
WRITE
READ D Count = 2
Load New Read Address D Count = 0 Always READ D Count = 2
Load New Write Address D Count = 0 WRITE D Count = 2 Always
WRITE D Count = 2
DDR Read D Count = D Count + 1 READ D Count = 1
DDR Write D Count = D Count + 1 WRITE D Count = 1
Always
Always
Increment Read Address
Increment Write Address
Notes: 1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R = Low, "READ" refers to read inactive status with R = High. The same is true for "WRITE" and "WRITE". 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K.
Rev: 1.01a 2/2006
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Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature
Value
-0.5 to 2.9 -0.5 to VDD -0.5 to VDDQ -0.5 to VDDQ +0.5 ( 2.9 V max.) -0.5 to VDDQ +0.5 ( 2.9 V max.) +/-100 +/-100 125 -55 to 125
Unit
V V V V V mA dc mA dc
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage I/O Supply Voltage Reference Voltage
Symbol
VDD VDDQ VREF
Min.
1.7 1.4 0.68
Typ.
1.8 1.5 --
Max.
1.9 VDD 0.95
Unit
V V V
Notes: 1. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. 2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
Operating Temperature Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Rev: 1.01a 2/2006
18/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low
Symbol
VIH (dc) VIL (dc)
Min
VREF + 0.1 -0.3
Max
VDD + 0.3 VREF - 0.1
Units
V V
Notes
1 1
Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is VREF 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min)DC = -0.3 V, VIL(Min)AC = -1.5 V (pulse width 3 ns). 4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width 3 ns).
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 200 -- --
Max
-- VREF - 200 5% VREF (DC)
Units
mV mV mV
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKHKH VDD + 1.0 V
VSS 50% VSS - 1.0 V 20% tKHKH
50% VDD
VIL
Rev: 1.01a 2/2006
19/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Input Capacitance Output Capacitance Clock Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT CCLK
Test conditions
VIN = 0 V VOUT = 0 V VIN = 0 V
Typ.
4 6 5
Max.
5 7 6
Unit
pF pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
1.25 V 0.25 V 2 V/ns 0.75 V VDDQ/2
AC Test Load Diagram
DQ 50 VT = VDDQ/2 RQ = 250 (HSTL I/O) VREF = 0.75 V
Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Doff Output Leakage Current
Symbol
IIL IINDOFF IOL
Test Conditions
VIN = 0 to VDD VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDDQ
Min.
-2 uA -2 uA -2 uA -2 uA
Max
2 uA 2 uA 2 uA 2 uA
Notes
Rev: 1.01a 2/2006
20/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 Vss
Max.
VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/- 15% @ VOH = VDDQ/2 (for: 175 RQ 350). 2. IOL = (VDDQ/2) / (RQ/5) +/- 15% @ VOL = VDDQ/2 (for: 175 RQ 350). 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = -1.0 mA 6. IOL = 1.0 mA
Operating Currents
-333 Parameter Symbol Test Conditions
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-300
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-250
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-200
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-167
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
Notes
Operating Current (x36): DDR Operating Current (x18): DDR Operating Current (x9): DDR Operating Current (x8): DDR
IDD IDD IDD IDD
VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min Device deselected, IOUT = 0 mA, f = Max, All Inputs 0.2 V or VDD - 0.2 V
2, 3 2, 3 2, 3 2, 3
Standby Current (NOP): DDR
ISB1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2, 4
Notes:
1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed.
Rev: 1.01a 2/2006
21/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics
Parameter Clock
K, K Clock Cycle Time C, C Clock Cycle Time tKC Variable K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse Width K to K High C to C High K, K Clock High to C, C Clock High DLL Lock Time K Static to DLL reset tKHKH tCHCH tKCVar tKHKL tCHCL tKLKH tCLCH tKHKH tKHCH tKCLock tKCReset tKHQV tCHQV tKHQX tCHQX tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX tKHQZ tCHQZ tKHQX1 tCHQX1 tAVKH tIVKH tDVKH 3.0 -- 1.2 1.2 1.35 0 1024 30 3.5 0.2 -- -- -- 1.30 -- -- 3.3 -- 1.32 1.32 1.49 0 1024 30 4.2 0.2 -- -- -- 1.45 -- -- 4.0 -- 1.6 1.6 1.8 0 1024 30 6.3 0.2 -- -- -- 1.8 -- -- 5.0 -- 2.0 2.0 2.2 0 1024 30 7.88 0.2 -- -- -- 2.3 -- -- 6.0 -- 2.4 2.4 2.7 0 1024 30 8.4 0.2 -- -- -- 2.8 -- -- ns ns ns ns ns ns cycle ns 6 5
Symbol
-333 Min Max Min
-300 Max
-250 Min Max
-200 Min Max Min
-167 Max
Units
Notes
Output Times
K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold CQ, CQ High Output Valid CQ, CQ High Output Hold K Clock High to Data Output High-Z C Clock High to Data Output High-Z K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z -- -0.45 -- -0.45 -- -0.25 -- -0.45 0.45 -- 0.45 -- 0.25 -- 0.45 -- -- -0.45 -- -0.45 -- -0.27 -- -0.45 0.45 -- 0.45 -- 0.27 -- 0.45 -- -- -0.45 -- -0.45 -- -0.30 -- -0.45 0.45 -- 0.45 -- 0.30 -- 0.45 -- -- -0.45 -- -0.45 -- -0.35 -- -0.45 0.45 -- 0.45 -- 0.35 -- 0.45 -- -- -0.5 -- -0.5 -- -0.40 -- -0.5 0.5 -- 0.5 -- 0.40 -- 0.5 -- ns ns ns ns ns ns ns ns 7 7 3 3 3 3
Setup Times
Address Input Setup Time Control Input Setup Time Data Input Setup Time 0.4 0.4 0.28 -- -- -- 0.4 0.4 0.3 -- -- -- 0.5 0.5 0.35 -- -- -- 0.6 0.6 0.4 -- -- -- 0.7 0.7 0.5 -- -- -- ns ns ns 2
Rev: 1.01a 2/2006
22/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics (Continued)
Parameter Hold Times
Address Input Hold Time Control Input Hold Time Data Input Hold Time tKHAX tKHIX tKHDX 0.4 0.4 0.28 -- -- -- 0.4 0.4 0.3 -- -- -- 0.5 0.5 0.35 -- -- -- 0.6 0.6 0.4 -- -- -- 0.7 0.7 0.5 -- -- -- ns ns ns
Symbol
-333 Min Max Min
-300 Max
-250 Min Max
-200 Min Max Min
-167 Max
Units
Notes
Notes:
1. 2. 3. 4. All Address inputs must meet the specified setup and hold times for all latching clock edges. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). If C, C are tied high, K, K become the references for C, C timing parameters To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is very tightly controlled to data valid/data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations.
5. 6. 7.
Rev: 1.01a 2/2006
23/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
K and K Controlled Read-Write-Read Timing Diagram
Read A KHKL KHKH KLKH Write B NOP Write C Read D Write E NOP
Rev: 1.01a 2/2006
KHKHbar AVKH A KHIX IVKH B C D E KHIX IVKH KHIX IVKH B DVKH B KHQX1 KHQV A A+1 A+2 A+3 KHQX D D+1 D+2 B+1 B+2 B+3 C KHQZ KHDX C+1 C+2 C+3 E E+1 B+1 B+2 B+3 C C+1 C+2 C+3 E E+1 KHCQX KHCQV CQHQX KHCQX KHCQV CQHQV
K
K
Address
R
W
24/29
BWx
D
Q
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CQ
CQ
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
(c) 2005, GSI Technology
C and C Controlled Read-Write-Read Timing Diagram
Read A KHKL KHKH KLKH NOP Read B Write C NOP Write D NOP
Rev: 1.01a 2/2006
KHKHbar AVKH KHAX A IVKH KHIX B C D IVKH KHIX IVKH C KHDX C C+1 C+2 C+1 C+2 DVKH C+3 D D+1 D KHIX C+3 D D+1 D CHQV CHQX1 A CHCQV CHCQX CQHQX A+1 CHQX A+2 A+3 B B+1 B+2 B+3 CHQZ CHCQX CHCQX CQHQV
K
K
Address
R
W
25/29
BWx
D
C
C
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q
CQ
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
CQ
(c) 2005, GSI Technology
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Package Dimensions--165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW O0.10 M C O0.25 M C A B O0.40~0.60 (165x)
A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 B 0.20(4x) 150.05 1.0
170.05
14.0
A
Rev: 1.01a 2/2006
0.36~0.46 1.50 MAX.
C
SEATING PLANE
0.20 C
26/29
1.0
1.0
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaQuad-II SRAM Org
8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18
Part Number1
GS8662D08E-333 GS8662D08E-300 GS8662D08E-250 GS8662D08E-200 GS8662D08E-167 GS8662D08E-333I GS8662D08E-300I GS8662D08E-250I GS8662D08E-200I GS8662D08E-167I GS8662D09E-333 GS8662D09E-300 GS8662D09E-250 GS8662D09E-200 GS8662D09E-167 GS8662D09E-333I GS8662D09E-300I GS8662D09E-250I GS8662D09E-200I GS8662D09E-167I GS8662D18E-333 GS8662D18E-300 GS8662D18E-250 GS8662D18E-200 GS8662D18E-167 GS8662D18E-333I GS8662D18E-300I GS8662D18E-250I GS8662D18E-200I GS8662D18E-167I
Type
SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167
TA3
C C C C C I I I I I C C C C C I I I I I C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01a 2/2006
27/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaQuad-II SRAM Org
2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9
Part Number1
GS8662D36E-333 GS8662D36E-300 GS8662D36E-250 GS8662D36E-200 GS8662D36E-167 GS8662D36E-333I GS8662D36E-300I GS8662D36E-250I GS8662D36E-200I GS8662D36E-167I GS8662D08E-333 GS8662D08GE-300 GS8662D08GE-250 GS8662D08GE-200 GS8662D08GE-167 GS8662D08GE-333I GS8662D08GE-300I GS8662D08GE-250I GS8662D08GE-200I GS8662D08GE-167I GS8662D09GE-333 GS8662D09GE-300 GS8662D09GE-250 GS8662D09GE-200 GS8662D09GE-167 GS8662D09GE-333I GS8662D09GE-300I GS8662D09GE-250I GS8662D09GE-200I GS8662D09GE-167I
Type
SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167
TA3
C C C C C I I I I I C C C C C I I I I I C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01a 2/2006
28/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662D08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaQuad-II SRAM Org
4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36
Part Number1
GS8662D18GE-333 GS8662D18GE-300 GS8662D18GE-250 GS8662D18GE-200 GS8662D18GE-167 GS8662D18GE-333I GS8662D18GE-300I GS8662D18GE-250I GS8662D18GE-200I GS8662D18GE-167I GS8662D36GE-333 GS8662D36GE-300 GS8662D36GE-250 GS8662D36GE-200 GS8662D36GE-167 GS8662D36GE-333I GS8662D36GE-300I GS8662D36GE-250I GS8662D36GE-200I GS8662D36GE-167I
Type
SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM
Package
RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167
TA3
C C C C C I I I I I C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01a 2/2006
29/29
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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